In modern complementary metal-oxide-semiconductor (CMOS) technology, parasitic transistor gate electrode capacitance is an ever more significant limiter of device performance. With device scaling, reductions in feature pitch continue to reduce distances between electrical nodes of a physical transistor. The introduction of high-k gate dielectrics may also adversely impact parasitic capacitances, for example where fabrication of the high-k gate dielectrics results in high-k films in regions other than at the interface between a transistor channel and the gate electrode. Furthermore, in addition to scaling and new materials introductions, structure geometries are now changing dramatically as the microelectronics industry now transitions from a planar to a non-planar field effect transistor (i.e., Tri-gate or FinFET). Pioneers of non-planar transistor technology are now developing second generation non-planar devices.
Techniques to reduce parasitic gate electrode capacitance are therefore advantageous. Furthermore, because gate electrodes for a given IC chip are typically all of a same z-height, unlike lithographically defined x and y dimensions of the gate electrode, transistor-level z-height control is also advantageous for selective tuning of gate electrode properties.